![\"ATxmega128A1U\"](\"https:\/\/ok2jnj.ok2kld.cz\/ok2jnj\/wp-content\/uploads\/2016\/04\/ATxmega128A1U.png\")
<\/a><\/p>\nProcesor lze koupit v \u010cR nap\u0159. u Farnell<\/a><\/span>. Jako v\u00fdvojov\u00e9 prost\u0159ed\u00ed pou\u017e\u00edv\u00e1m AVR studio. Procesor m\u016f\u017eeme naprogramovat b\u011b\u017en\u00fdmi p\u0159\u00edpravky, jako je Dragon, AVRISP MK2 atd. Pro komunikaci p\u0159i programov\u00e1n\u00ed nen\u00ed pou\u017eit kan\u00e1l SPI, ale procesor m\u00e1 pin PDI_DATA, kter\u00fd se p\u0159ipoj\u00ed na prvn\u00ed pin \u0161esti-pinov\u00e9ho konektoru program\u00e1toru. D\u00e1le je nutn\u00fd sign\u00e1l RESET, VCC a GND. Maxim\u00e1ln\u00ed kmito\u010det procesoru je 32MHz, co\u017e je dvojn\u00e1sobek proti ATmega128. N\u011bkter\u00e9 instrukce pot\u0159ebuj\u00ed men\u0161\u00ed po\u010det cykl\u016f a hlavn\u011b, procesor m\u00e1 integrov\u00e1no velk\u00e9 mno\u017estv\u00ed hardwarov\u00fdch modul\u016f, kter\u00e9 zjednodu\u0161uj\u00ed program.<\/p>\n U obvod\u016f rodiny ATmega je obvykl\u00e9, \u017ee ka\u017ed\u00fd procesor m\u00e1 sv\u016fj datov\u00fd list – dokument PDF, ve kter\u00e9 jsou v\u0161echny informace o obvodu, popis vlastnost\u00ed, registr\u016f, zp\u016fsob nastaven\u00ed v\u0161ech periferi\u00ed. U ATxmega jsem si musel zvyknout na to, \u017ee dokumenty jsou dva. Jedn\u00edm je manu\u00e1l ke v\u0161em procesor\u016fm skupiny – skupiny jsou \u010dty\u0159i, ozna\u010deny p\u00edsmeny A, B, C a D. V manu\u00e1lu jsou v\u0161echny informace, kter\u00e9 jsou spole\u010dn\u00e9 pro procesory z jedn\u00e9 skupiny. Jsou pops\u00e1ny periferie a zp\u016fsob jejich ovl\u00e1d\u00e1n\u00ed prost\u0159ednictv\u00edm registr\u016f. V dokumentu ke konkr\u00e9tn\u00edmu procesoru je pops\u00e1no p\u0159ipojen\u00ed pin\u016f a elektrick\u00e9 vlastnosti obvodu. P\u0159i p\u0159echodu z ATmega je to nezvykl\u00e9, ale ve v\u00fdsledku v\u00fdhodn\u00e9 uspo\u0159\u00e1d\u00e1n\u00ed informac\u00ed. D\u00e1le je na webu atmel.com<\/a><\/span> k dispozici sada dokument\u016f, kter\u00e9 popisuj\u00ed pou\u017eit\u00ed jednotliv\u00fdch \u010d\u00e1st\u00ed procesoru.<\/p>\n Zdroj hodinov\u00e9ho sign\u00e1lu u procesor\u016f rodiny ATxmega nen\u00ed ovl\u00e1d\u00e1n pomoc\u00ed bit\u016f pojistek, jak je zvykem u ATmega. Hodinov\u00fd kmito\u010det u procesor\u016f xmega je \u0159\u00edzen programov\u011b, prost\u0159ednictv\u00edm n\u011bkolika registr\u016f. Po resetu je v\u017edy p\u0159ipojen intern\u00ed RC oscil\u00e1tor 2MHz. Jin\u00fd zdroj sign\u00e1lu m\u016f\u017eeme p\u0159ipojit nastaven\u00edm registr\u016f. Je mo\u017enost p\u0159ipojit intern\u00ed 32MHz oscil\u00e1tor, 32,768kHz, nebo extern\u00ed krystal. Maxim\u00e1ln\u00ed kmito\u010det procesoru je 32MHz, n\u011bkter\u00e9 periferie mohou b\u011b\u017eet na vy\u0161\u0161\u00edm kmito\u010dtu. Obvod procesoru sleduje chod oscil\u00e1tor\u016f a zobrazuje jej na registru OSC_STATUS. Tak\u017ee p\u0159ed p\u0159ipojen\u00edm oscil\u00e1toru je mo\u017en\u00e9 a z\u00e1rove\u0148 vhodn\u00e9 zjistit, jestli oscil\u00e1tor funguje. Chod procesoru nelze zablokovat \u0161patn\u00fdm naprogramov\u00e1n\u00edm pojistek, jako u ATmega.<\/p>\n Registr OSC_CTRL spou\u0161t\u00ed oscil\u00e1tory, registr OCS_STATUS zobrazuje jejich spr\u00e1vnou funkci. Registr CLK_CTRL p\u0159ipoj\u00ed oscil\u00e1tor k procesoru. Z\u00e1pis do tohoto registru je chr\u00e1n\u011bn t\u00edm, \u017ee je nutn\u00e9 nap\u0159ed zapsat hodnotu 0xD8 do CCP. Potom je z\u00e1pis do chr\u00e1n\u011bn\u00fdch registr\u016f umo\u017en\u011bn po dobu \u010dty\u0159 cykl\u016f. V\u0161echny p\u0159eru\u0161en\u00ed jsou b\u011bhem t\u00e9to doby zak\u00e1z\u00e1ny. Nevy\u0159\u00edzen\u00e9 p\u0159eru\u0161en\u00ed bude zpracov\u00e1no po ukon\u010den\u00ed t\u00e9to doby.<\/p>\n Popsan\u00e9 uspo\u0159\u00e1d\u00e1n\u00ed zdroj\u016f hodinov\u00e9ho sign\u00e1lu umo\u017e\u0148uje sestavit mnoho variant \u00fasporn\u00fdch re\u017eim\u016f, dle aktu\u00e1ln\u00ed pot\u0159eby programovan\u00e9 aplikace.<\/p>\n V\u00a0ATmega existuj\u00ed t\u0159i registry, kter\u00e9 ovl\u00e1daj\u00ed I\/O pin portu. Jsou to DDRx, PINx a PORTx. V\u00a0Xmega je tento koncept roz\u0161\u00ed\u0159en, co\u017e umo\u017e\u0148uje v\u011bt\u0161\u00ed rozsah pou\u017eit\u00ed. Mo\u017enosti jsou podobn\u00e9 jako u procesor\u016f ARM, nebo STM32. Jednou z d\u016fle\u017eit\u00fdch v\u011bc\u00ed je alternativn\u00ed funkce I\/O pinu. To umo\u017e\u0148uje pou\u017e\u00edt univerz\u00e1ln\u00ed I\/O pin pro integrovan\u00e9 hardwarov\u00e9 moduly, jako je USART, I2C, SPI a podobn\u011b. Xmega nav\u00edc m\u016f\u017ee tyto alternativn\u00ed funkce softwarov\u011b p\u0159em\u00eds\u0165ovat z\u00a0jednoho pinu na druh\u00fd.<\/p>\n I\/O porty jsou pojmenov\u00e1ny jako PORTA, PORTB atd., p\u0159i\u010dem\u017e jednotliv\u00e9 piny jsou pojmenov\u00e1ny PA6, PB4\u2026 tak\u017ee existuje ur\u010dit\u00e1 podobnost se star\u0161\u00edmi ATmega obvody, pokud jde o pojmenov\u00e1n\u00ed port\u016f a jednotliv\u00fdch pin\u016f. Ke ka\u017ed\u00e9mu portu je p\u0159i\u0159azeno n\u011bkolik registr\u016f:<\/p>\n Registr ovl\u00e1d\u00e1 vlastnosti jednoho pinu v\u00a0portu. Tak\u017ee ke ka\u017ed\u00e9mu portu je p\u0159i\u0159azeno osum t\u011bchto registr\u016f. Z\u00e1pis nap\u0159. PORTD_PIN1CTRL = 0x01;<\/p>\n Skupina bit\u016f OPC p\u0159ipojuje rezistory, skupina bit\u016f ISC \u0159\u00edd\u00ed p\u0159eru\u0161en\u00ed. ISC=111 odpoj\u00ed pin \u00fapln\u011b.<\/p>\n Programovateln\u00fd, v\u00edce\u00farov\u0148ov\u00fd ovlada\u010d p\u0159eru\u0161en\u00ed PMIC, nastavuje priority po\u017eadavk\u016f na p\u0159eru\u0161en\u00ed. Stejn\u011b jako u jin\u00fdch procesor\u016f by m\u011bl b\u00fdt nastaven p\u0159ed glob\u00e1ln\u00edm povolen\u00edm p\u0159eru\u0161en\u00ed, pomoc\u00ed bitu SREG.<\/p>\n Je-li povoleno p\u0159eru\u0161en\u00ed, PMIC p\u0159ij\u00edm\u00e1 po\u017eadavek na p\u0159eru\u0161en\u00ed a ten bu\u010f vykon\u00e1, nebo \u010dek\u00e1, na z\u00e1klad\u011b nastaven\u00fdch priorit. Po vykon\u00e1n\u00ed po\u017eadavku na p\u0159eru\u0161en\u00ed, se PMIC vr\u00e1t\u00ed na p\u016fvodn\u00ed \u00farove\u0148, nebo do stavu p\u0159ed vol\u00e1n\u00edm p\u0159eru\u0161en\u00ed.<\/p>\n To znamen\u00e1, \u017ee p\u0159eru\u0161en\u00ed s\u00a0vy\u0161\u0161\u00ed prioritou, p\u0159eru\u0161\u00ed vykon\u00e1v\u00e1n\u00ed programu p\u0159eru\u0161en\u00ed s\u00a0ni\u017e\u0161\u00ed prioritou. Po zpracov\u00e1n\u00ed p\u0159eru\u0161en\u00ed s\u00a0vy\u0161\u0161\u00ed prioritou, bude zpracov\u00e1no dal\u0161\u00ed p\u0159eru\u0161en\u00ed. V\u00a0z\u00e1kladn\u00edm nastaven\u00ed maj\u00ed vektory s\u00a0nejni\u017e\u0161\u00ed adresou nejvy\u0161\u0161\u00ed prioritu. Nap\u0159\u00edklad, vektor p\u0159eru\u0161en\u00ed Reset m\u00e1 nejvy\u0161\u0161\u00ed prioritu a nejni\u017e\u0161\u00ed adresu.<\/p>\n V\u00a0Xmega existuj\u00ed dva typy p\u0159eru\u0161en\u00ed, to jsou statick\u00e9 a dynamick\u00e9. Statick\u00e9 p\u0159eru\u0161en\u00ed jsou ty, kter\u00e9 maj\u00ed pevnou adresu vektoru a z\u00e1rove\u0148 n\u00edzkou prioritu p\u0159eru\u0161en\u00ed. Dynamick\u00e9 chov\u00e1n\u00ed je dosa\u017eeno Round-robin Scheduling (RRS) technikou. RRS zaji\u0161\u0165uje, \u017ee p\u0159eru\u0161en\u00ed n\u00edzk\u00e9 \u00farovn\u011b nen\u00ed vynech\u00e1no. Pou\u017eije-li se tato technika, pak posledn\u00ed vyvolan\u00e9 p\u0159eru\u0161en\u00ed bude m\u00edt nejni\u017e\u0161\u00ed prioritu. V\u00a0n\u00edzk\u00e9 \u00farovni p\u0159eru\u0161en\u00ed existuje mechanismus, kter\u00fd zajist\u00ed, \u017ee v\u0161echny p\u0159eru\u0161en\u00ed jsou zavol\u00e1ny v\u00a0ur\u010dit\u00e9m \u010dasov\u00e9m horizontu.<\/p>\n","protected":false},"excerpt":{"rendered":" P\u0159i seznamov\u00e1n\u00ed s TFT displejem jsem dosp\u011bl k n\u00e1zoru, \u017ee procesory \u0159ady ATmega maj\u00ed pro tuto aplikaci mal\u00fd v\u00fdkon. Pokud<\/p>\n","protected":false},"author":1,"featured_media":827,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[4],"tags":[136,138,139],"class_list":["post-824","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-programovani","tag-atmel","tag-atxmega","tag-interrupt-atxmega"],"yoast_head":"\nDokumentace k procesoru<\/h2>\n
Zdroj hodinov\u00e9ho sign\u00e1lu<\/h2>\n
\u00a0\u00a0\u00a0 OSC_CTRL |= OSC_RC32MEN_bm;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\/\/ spusti 32HMz oscilator\r\n\u00a0\u00a0 \u00a0while(!(OSC_STATUS & OSC_RC32MRDY_bm));\u00a0\u00a0 \u00a0\/\/ ceka, az bude oscilator aktivni\r\n\u00a0\u00a0 \u00a0CCP = CCP_IOREG_gc;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\/\/ zapis hodnoty 0xD8 do registru, ktery umozni dalsi zapis\r\n\u00a0\u00a0 \u00a0CLK_CTRL = CLK_SCLKSEL_RC32M_gc;\u00a0\u00a0 \u00a0\u00a0 \u00a0 \u00a0\/\/ pripojeni 32MHz oscilatoru<\/pre>\n
Ovl\u00e1d\u00e1n\u00ed I\/O port\u016f procesoru ATxmega128<\/h2>\n
\n
Registr PINnCTRL<\/h3>\n
\n
<\/a><\/p>\n<\/a><\/h4>\nP\u0159\u00edklad nastaven\u00ed I\/O portu<\/h3>\n
\u00a0\u00a0\u00a0 PORTE_OUT = 0x00;\r\n\u00a0\u00a0 \u00a0PORTE_DIR = 0x00;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\/\/ port bude vstupni\r\n\u00a0\u00a0 \u00a0PORTE_PIN0CTRL = 0b10011001;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\/\/ citlivy na vzestupnou tlacitko PE0\r\n\u00a0\u00a0 \u00a0PORTE_PIN1CTRL = 0b10011001;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\/\/ citlivy na vzestupnou tlacitko PE1<\/pre>\n
Extern\u00ed p\u0159eru\u0161en\u00ed u ATxmega<\/h2>\n
PMIC a priorita p\u0159eru\u0161en\u00ed<\/h3>\n